FPGA-Specific Custom Arithmetic Datapath Design

This paper presents FloPoCo, a framework for easily designing custom arithmetic datapaths for FPGAs. Its main features are: an important basis of highly optimized arithmetic operators, a unique methodology for frequency-directed pipelining the designed circuits and a flexible test-bench generation suite for numerically validating the designs. The framework was tested for designing several complex arithmetic operators, this paper presenting the architecture and results for the exponential operator. Synthesis results capture the designed operator’s flexibility: automatically optimized for several Altera and Xilinx FPGAs, wide range of target frequencies and several precisions ranging from single to quadruple precision. Keywords-FloPoCo; framework; arithmetic circuit; pipelining; flexibility;